Welcome to UVM 1.0 EA and to UVMWorld.org
This is the first of an ongoing series of posts related to EDA Standards activities. In some cases I’ll be highlighting “standards happenings”, while in other posts I’ll speak out about various...
View ArticleKaren Bartleson’s Book & The Nature of Standards Groups
Karen Bartleson’s book on Standards, for which I was pleased to write a blurb for its front pages, is now out: http://synopsysoc.org/thestandardsgame. As I indicate in my blurb, Karen’s book does a...
View ArticleNew Items of Interest On UVMWorld.org
In an earlier blog entry, I pointed readers to the new UVMWorld.org site. I’d like to do this again in order to highlight two recently added items that will be of interest to the UVM community. The...
View ArticleDAC And EDA Standards
DAC has always been intertwined with Standards for me. In fact, the main reason I attended my first DAC in Las Vegas in 1986 was to attend the 1076 VHDL face-to-face meetings that were held before...
View ArticleClik here to view.
UVM At DAC
The recently completed 47th DAC in Anaheim proved to be the “coming out party” for Accellera’s nascent Universal Verification Methodology (UVM) efforts. Of course, there has been a core of people who...
View ArticleOpen Source, Open Standards And UVM
In a previous article, I mentioned the Accellera DAC Breakfast panel on UVM. The moderator of the panel, Gabe Moretti, posed the following dilemma: UVM is to be released as open source, but it is also...
View ArticleBackwards Compatability Between UVM 1.0EA And UVM 1.0
During the recently completed DAC I was repeatedly asked about the expected backwards compatibility (or lack thereof) between the currently released UVM 1.0EA and the to-be-released UVM 1.0. Why...
View ArticleClik here to view.
Japan & SystemC
With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end...
View Article
